1. Field of the Invention
The present invention relates to a tightly coupled multiprocessor system in which a main storage is shared by a plurality of processors, and to techniques effective for the application to cache coherency control.
2. Description of the Related Art
It is common for a presently used processor module to have a high speed internal cache memory, which temporarily stores data transferred to and from an external main storage or the like, in order to speed up the operation. In a tightly coupled multiprocessor system having a main storage which is shared by a plurality of processors each having a cache memory, data in the main storage at the same address is dispersively present in cache memories of a plurality of processors. This dispersed data is updated independently at each processor if write-back caching is performed in which updated write data is also stored in the main storage via the cache memory. In this case, there is a possibility that the data in the cache memory at each processor is different (dirty) from the data in the main storage at the same address. Therefore, if any one of processors issues a read request to the main storage, it becomes essential to perform cache coherency control in order to ensure the correct operation of the system, i.e., to ensure time sequential integrity (coherency) of data in the cache memory of each processor and in the main storage, in other words, to ensure that read data is the newest data.
Typical techniques of a cache coherency control scheme for such a tightly coupled multiprocessor system are disclosed in various documents such as M. S. Papamacros and J. H. Paten, "A Low-overhead Coherence Solution for Multiprocessors with Private Cache Memories", Proc. the 11th International Symposium on Computer Architecture, 1984. pp. 348-354.
This document defines the following cache states of a multiprocessor system having a plurality of processor modules sharing a main storage (memory module) via a bus. These cache states include: (a) Invalid (data is invalid); (b) Shared-Unmodified (data is also present in the cache memory of another processor and is the same as the data in the main storage); (c) Exclusive-Modified (data is present only in the cache memory in concern and not the same as the data in the main storage); and (d) Exclusive-Unmodified (data is present only in the cache memory in concern and is the same as the data in the main storage).
When any one of processor modules issues a read request and the data is not stored in the cache memory of this processor module (read miss), a Read Request Tx (Transaction) is broadcast via the bus to the memory module (MM) and processor modules (PMs). If any one of PM cache memories hits, the data is returned from this PM to the requesting PM and at the same time the data is written in MM. If any one of PM cache memories does not hit, data is returned from MM.
If a data line in the cache memory to be replaced (already stored data is driven out in order to form an empty area in the cache memory) is Exclusive-Modified, this is reflected upon MM by sending a Write Back Tx to the bus.